1. Field of the Invention
The present invention relates to a method for fabricating packages adapted to appropriately arrange semiconductor packages and to appropriately couple them while protecting them, and more particularly to a method for fabricating chip size packages using a lamination process.
2. Description of the Prior Art
Packaging techniques are techniques widely used for fabricating a variety of systems, which techniques involve the entire process from the fabrication of semiconductor devices to the manufacture of final products using the fabricated semiconductor devices.
Recently, semiconductor techniques have been rapidly developed. In particular, such semiconductor techniques have been developed to a degree capable of obtaining an integration of one million cells or more, an increase in the number of I/O pins in the case of non-memory devices, an increase in die size, an increased heat discharge ability, and a high electrical performance. However, electronic packaging techniques used to package semiconductor devices have been slowly developed, as compared to the rapid developments in the semiconductor techniques.
Electronic packaging techniques are important in determining the performance, size, costs and reliability of final electronic products. In particular, super-micro packages are essential elements for recently developed electronic appliances, such as computers, data communication systems, mobile communication systems and high-grade home appliances, configured to ensure a high electrical performance, super-micro/highly dense structure, low power consumption, multiple functions, super-high signal processing, and permanent reliability.
For example, the application of chip size packages, which are a kind of such super-micro packages, is extended to PC cards, card-size personal computers, compact global position system receivers, camcorders, personal digital assistants, notebook computers, and telephone handsets.
Such chip size packages include lead-on-chip (LOC) type chip size packages adapted to package memory chips and micro ball grid array (BGA) type chip size packages adapted to package non-memory chips. LOC chip size packages are mainly used for packages of a 16 Mega grade or greater. Micro BGA chip size packages are fabricated using a combination of a BGA technique using solder balls and a chip size packaging technique. In addition, there are a variety of chip size packaging techniques for packaging non-memory chips. However, there is no specified standard for chip size packaging techniques.
U.S. Pat. No. 5,293,067 discloses an "integrated circuit chip carrier" used to fabricate semiconductor packages. In accordance with this patent, a patterned package carrier is first fabricated. A semiconductor chip is mounted on the patterned package carrier by means of solder balls, thereby fabricating a semiconductor package. However, this technique requires complicated processes because a solder ball forming process is used twice in accordance with the patent. Furthermore, this technique exhibits very low reliability because the chip is exposed. In addition, the required processes are expensive. This results in a difficulty in mass production and a very low marketability.